An industry-first 20nm tapeout signals the dawn of an ASIC-class programmable architecture, with benefits for digital video and broadcast, OTN networks and wireless communications, writes Mike Santarini


Author: Mike Santarini, publisher, Xcell Journal

Building on its breakout move at 28 nanometers (nm), Xilinx has announced two industry firsts at the 20nm node. Xilinx is the first merchant chip company to tape out a 20nm device. The new device will be the first that Xilinx will bring to market using its UltraScale technology — the programmable industry’s first architecture that is ASIC (application-specific integrated circuit) class.

The UltraScale architecture takes full advantage of the electronic design automation (EDA) technologies in the Vivado Design Suite, enabling customers to quickly create a new generation of All Programmable innovations. The move continues the Generation Ahead advantage over competitors that began at 28nm, when Xilinx delivered two first-of-their-kind devices: the Zynq-7000 All Programmable SoC and Virtex-7 3D ICs.

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“Xilinx was the first company to deliver 28nm devices and at 20nm, we’ve maintained the industry’s most aggressive tapeout schedule,” said Steve Glaser, senior vice president of marketing and corporate strategy at Xilinx. “Our hard work is paying off and we’re clearly a year ahead of our competition in delivering high-end devices and half a year ahead delivering mid-range devices.”

But as Xilinx did at 28nm, the company is also adding some industry-first innovations to its new portfolio. Among the first the company is revealing is the new UltraScale architecture, which it will be implementing at 20nm, 16nm FinFET and beyond. “It’s the first programmable architecture to enable users to implement ASIC-class designs using All Programmable devices,” said Glaser. “The UltraScale architecture enables Xilinx to deliver 20-nm and FinFET 16nm All Programmable devices with massive I/O and memory bandwidth, the fastest packet processing, the fastest DSP processing, ASIC-like clocking, power management and multilevel security.”


Fig 1: UltraScale architecture enables massive I/O and memory bandwidth, fast packet processing and DSP processing

The UltraScale architecture includes hundreds of structural enhancements, many of which Xilinx would  have been unable to fully implement had it not already developed its Vivado Design Suite, which brings leading-edge EDA tool capabilities to Xilinx customers. For example, Vivado’s advanced placement-and-routing capabilities enable users to take full advantage of UltraScale’s massive data-processing abilities, so that design teams will be able to achieve better than 90 per cent utilisation in UltraScale devices while also hitting ambitious performance and power targets.

This utilisation is far beyond what is possible with competing devices, which today require users to trade off performance for utilisation. Customers are thus forced to move to that vendor’s bigger and more expensive device, only to find they have to slow down the clock yet again to meet system power goals.

This problem didn ot plague Xilinx at the 28nm process node thanks to Xilinx’s routing architecture. Nor will it be an issue at 20nm, because the UltraScale architecture can implement massive data flow for wide buses to help customers develop systems with multiterabit throughput and with minimal latency.

The UltraScale architecture co-optimised with Vivado results in highly optimised critical paths with built-in, high-speed memory cascading to remove bottlenecks in DSP and packet processing. Enhanced DSP subsystems combine critical-path optimisation with new 27×18-bit multipliers and dual adders that enable a massive jump in fixed- and IEEE-754 floating-point arithmetic performance and efficiency.

The wide-memory implementation also applies to UltraScale 3D ICs, which will see a step-function improvement in interdie bandwidth for even higher overall performance.

UltraScale devices feature further I/O and memory-bandwidth enhancements, including support for next-generation memory interfacing that offers a dramatic reduction in latency and optimised I/O performance. The architecture offers multiple hardened, ASIC-class IP cores, including 10/100G Ethernet, Interlaken and PCIe.

The UltraScale architecture also enables multiregion clocking — a feature typically found only in ASIC-class devices. Multiregion clocking allows designers to build high-performance, low-power clock networks with extremely low clock skew in their systems.

The co-optimisation of the UltraScale architecture and Vivado also allows design teams to employ a wider variety of power-gating techniques across a wider range of functional elements in Xilinx’s 20nm All Programmable devices to achieve further power savings in their designs. Last but not least, UltraScale supports advanced approaches to AES bitstream decryption and authentication, key obfuscation and secure device programming to deliver best-in-class system security.


Fig 2: UltraScale architecture will speed the development of multiple types of next-generation systems, especially in wired and wireless communications (click to enlarge)

Glaser said that UltraScale devices will enable design teams to achieve even greater levels of system integration while maximising overall system performance, lowering total system power and reducing the overall BOM cost of their systems. “Building on what we did at 28nm, Xilinx at the 20nm and FinFET 16/14 nodes is raising the value proposition of our All Programmable technology far beyond the days when FPGAs were considered merely a nice alternative to logic devices,” he said. “Our unique system value is abundantly clear across a broad number of applications.”

Glaser said devices using Xilinx’s 20nm and FinFET 16nm UltraScale architecture squarely address a number of growth market segments, such as optical transport networking (OTN), high-performance computing in the network, digital video and wireless communications (see Figure 2). All of these sectors must address increasing requirements for performance, cost, lower power and massive integration.


The OTN market is currently undergoing a change to smarter networks, as data traffic dictates a massive buildout to create ever-more-advanced wired networking equipment that can move data from 100 Gbps today to 400 Gbps soon and, then, to 1 Tbps.

While the traditional business approach would be to simply throw massive amounts of newer and faster equipment at the problem, network operators are seeking smarter ways to build out their networks and to improve the networks they have installed while finding better ways to manage costs — all to vastly improve service and profitability.

For example, the data centre market is looking to software-defined networking (SDN) as a way to optimise network utilisation and cut costs. SDN will allow network managers to leverage the cloud and virtual networks to provide data access to any type of Internet-connected device. The hardware to enable these software-defined networks will have to be extremely flexible, reliable and high performance. Greater programmability coupled more tightly with processing will be mandatory.

While network manufacturing companies develop next-generation software-defined networks, their customers are constantly looking to prolong the life of existing equipment. Companies have implemented single-chip CFP2 optical modules in OTN switches with Xilinx 28nm Virtex-7 F580T 3D ICs to exponentially increase network bandwidth.

With UltraScale, Xilinx is introducing devices that enable further integration and innovation, allowing companies to create systems capable of driving multiple CFP4 optical modules for yet another exponential gain in data throughput (see Figure 3).


Fig 3 – UltraScale architecture will enable higher-performance, single-chip CFP4 modules that will improve the performance of existing OTN equipment (click to enlarge)

Digital video is another market facing a massive buildout. HDTV manufacturers and the supporting broadcast infrastructure are rapidly building TVs and broadcast infrastructure equipment (cameras, communications and production gear) for 1080p, 4k/2k and 8k video. TVs will not only need to conform to these upcoming standards, they must also be feature rich and reasonably priced. The market is extremely competitive, so having devices that can adjust to changing standards quickly and can help manufacturers differentiate their TVs is imperative.

While screen resolution and picture quality will increase greatly with the transition from 1080p to 4k/2k to 8k, TV customers will want ever thinner models. This means new TV designs will require even greater integration while achieving the performance, power and BOM cost requirements the consumer market demands.

While broadcast equipment will need to advance drastically to conform to the requirements for 4k/2k and 8k video, perhaps the biggest customer requirements for these systems will be flexibility and upgradability. Broadcast standards are ever evolving. Meanwhile, the equipment to support these standards is expensive and not easily swapped in and out.

As a result, broadcast companies are getting smarter about their buying and are making longevity and upgradability their top requirements. This makes equipment based on All Programmable devices a must-have for all sectors of the next-generation broadcast market, from the camera at the ballgame to the production equipment in the control room to the TV in your living room.

Figure 4 illustrates how a midrange Kintex UltraScale device will enable professional and ‘pro-sumer’ camera manufacturers to quickly bring to market new cameras with advanced capabilities for 4k/2k and 8k while dramatically cutting cost, size and weight.


Fig 4: UltraScale architecture will let professional and consumer-grade camera manufacturers bring 8k cameras to market sooner (click to enlarge)

Without a doubt, the most rapidly expanding business in electronics is mobile communications. With usage of mobile devices increasing tenfold over the last 10 years and projections for even more dramatic growth in the coming decade, carriers are scrambling to devise ways to woo customers to service plans in the face of increased competition.

Wireless coverage and network performance are key differentiators and so carriers are always looking for network equipment that is faster and can carry a vast amount of data quickly. They could, of course, buy more and more higher-performance basestations, but the infrastructure costs of building out and maintaining more equipment cuts into profitability, especially as competitors try to lure customers away by offering more cost-effective plans.

Very much like their counterparts in wired communications, wireless carriers are seeking smarter ways to run their business and are looking for innovative network architectures.

One such architecture, called cloud radio-access networks (C-RAN), will enable carriers to pool all the baseband processing resources that would normally be associated with multiple basestations and perform baseband processing in the cloud.

Carriers can automatically shift their resources to areas experiencing high demand, such as those near live sporting events, and then reallocate the processing to other areas as the crowd disperses. The result? Better quality of service for customers and a reduction in capital as well as operating expenditures for carriers, with improved profitability.

Creating viable C-RAN architectures requires highly sophisticated and highly flexible systems-on-chip that integrate high-speed I/O with parallel and serial processing. Xilinx’s UltraScale FPGAs and SoCs will play key roles in this buildout. The company is building UltraScale 20nm versions of its Kintex and Virtex All Programmable FPGAs, 3D ICs and Zynq All Programmable SoCs. The company is also developing Virtex UltraScale devices in TSMC’s FinFET 16 technology.,standards
  Author: Mike Santarini, publisher, Xcell Journal Building on its breakout move at 28 nanometers (nm), Xilinx has announced two industry firsts at the 20nm node. Xilinx is the first merchant chip company to tape out a 20nm device. The new device will be the first that Xilinx will bring to...